2015Unpublished venueRequires access

Low voltage bulk-driven CMOS inverter with lower delays

Maneesha Gupta, Bhawna Aggarwal, Priyanka Garg, Parish Aggarwal, Swati Jain

Open publisher page 2 citations

Abstract

In this paper, a low voltage bulk-driven CMOS inverter capable of operating at power supplies of ±0.9V using standard CMOS technologies is proposed. The proposed inverter gives not only smoother transient response with a lower delay, but also a sharper fall from high to low than its gate-driven counterpart. The proposed bulk-driven inverter is analysed for various regions of operation and simulated results using SPICE in 0.35μm CMOS technology are shown to demonstrate the effectiveness of the circuit.

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What this paper is about

In this paper, a low voltage bulk-driven CMOS inverter capable of operating at power supplies of ±0.9V using standard CMOS technologies is proposed. The proposed inverter gives not only smoother transient response with a lower delay, but also a sharper fall from high to low than its gate-driven counterpart. The proposed bulk-driven inverter is analysed for various regions of operation and simulated results using SPICE in 0.35μm CMOS technology are shown to demonstrate the effectiveness of the circuit.

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Available abstract

In this paper, a low voltage bulk-driven CMOS inverter capable of operating at power supplies of ±0.9V using standard CMOS technologies is proposed. The proposed inverter gives not only smoother transient response with a lower delay, but also a sharper fall from high to low than its gate-driven counterpart. The proposed bulk-driven inverter is analysed for various regions of operation and simulated results using SPICE in 0.35μm CMOS technology are shown to demonstrate the effectiveness of the circuit.

Key concepts: CMOS, Inverter, Spice, Electronic engineering, Transient (computer programming), Voltage, Logic gate, Electrical engineering

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