DESIGN AND VERIFICATION OF LOW POWER AREA EFFICIENT CARRY SELECT ADDER FOR 128 BIT

An adder is one of the key hardware blocks in most digital and high performance processors such as digital signal processors and microprocessors etc. With advances in technology, many researchers have tried and are trying to design adders which offer either of the following- high speed, low power consumption, regularity of layout and hence less area or even combination of them. Thus it makes the designs suitable for various high speed and low power VLSI implementations. However area and speed are two conflicting constraints. Hence as speed improves area increases. This paper provides the best trade off solution among both of them. Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. Different adder architectures like Carry Chain Adder, Carry- look Ahead Adder, Carry Select Adder and Carry Skip Adder for different operand size like 16-bit, 32-bit, 64- bit and 128 bit one of the adders which have less delay and minimum area (Carry Select Adder) is chosen. The design is developed by verilog HDL, synthesized in Xilinx ISE tool for Spartan6 FPGA. The results show that the modified SQRT CSLA has a slightly larger delay (only3.76%), but the area and power of the 128-bit modified SQRT CSLA are significantly reduced by 17.4% and 15.4% respectively. The power-delay product and also the area-delay product of the proposed design show a decrease for 16, 32, 64 and 128-bit sizes.