A comparative study on low-power and high speed Carry Select Adder

Adders are the basic building blocks of any processor or data path application. In adder design carry generation is the critical path. To reduce the power consumption of data path we need to reduce Area and number of transistors of the adder. Carry Select Adder is one of the fast adder used in many data path applications. In this paper Power consumption, area and delay of different carry select adders for 8bit, 16bit, 32bit, 64bit have been examined. A detailed comparative analysis has been done in Area, delay and power to all the Carry select adders. A new design based on D latch has reduced area, power And delay as compared with the regular SQRT CSLA. Power, delay and area have been calculated by using SYNOPSYS Design Vision tool. The results analysis shows that the new D latch based carry save adder CSLA structure is better than the regular SQRT CSLA.