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A 4.23-bit, 12.5 GS/s comparator for high speed flash ADC in BiCMOS technology

Mohammad Jafar Taghizadeh Marvast, Mohd Alauddin Mohd Ali

Open publisher page 4 citations

Abstract

A 4.23-bit, high speed comparator for high-speed flash analog-to-digital converter and X-band applications that can work at a sampling rate of 12.5GS/s is presented in this paper. This fully differential comparator consists of three stages using a new structure to improve its performance. The offset voltage of the designed comparator has been reduced by means of an active positive feedback. The BiCMOS positive feedback and a new structure as output circuit are used to improve sampling rate and performance of comparator. The analyses and simulation results were obtained by using BiCMOS parameters. The comparator can operate with a 1 V peak-to-peak input range consuming 1.09 mW. The predicted performance is verified by analyses and simulations using HSPICE tool.

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What this paper is about

A 4.23-bit, high speed comparator for high-speed flash analog-to-digital converter and X-band applications that can work at a sampling rate of 12.5GS/s is presented in this paper. This fully differential comparator consists of three stages using a new structure to improve its performance. The offset voltage of the designed comparator has been reduced by means of an active positive feedback. The BiCMOS positive feedback and a new structure as output circuit are used to improve sampling rate and performance of comparator. The analyses and simulation results were obtained by using BiCMOS parameters. The comparator can operate with a 1 V peak-to-peak input range consuming 1.09 mW. The predicted performance is verified by analyses and simulations using HSPICE tool.

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Available abstract

A 4.23-bit, high speed comparator for high-speed flash analog-to-digital converter and X-band applications that can work at a sampling rate of 12.5GS/s is presented in this paper. This fully differential comparator consists of three stages using a new structure to improve its performance. The offset voltage of the designed comparator has been reduced by means of an active positive feedback. The BiCMOS positive feedback and a new structure as output circuit are used to improve sampling rate and performance of comparator. The analyses and simulation results were obtained by using BiCMOS parameters. The comparator can operate with a 1 V peak-to-peak input range consuming 1.09 mW. The predicted performance is verified by analyses and simulations using HSPICE tool.

Key concepts: Comparator, Flash ADC, BiCMOS, Flash (photography), Computer science, Electrical engineering, Transistor, Physics

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