VLSI Implementation of Enhanced AES Cryptography

Advanced Encryption Standard (AES) is a Federal Information Processing Standard (FIPS) and categorized as Computer Security Standard. The AES algorithm is a block cipher that can encrypt and decrypt digital information. The AES algorithm is capable of using cryptographic keys of 128, 192 and 256 bits. The Rijndael cipher has been selected as the official Advanced Encryption Standard (AES) and it is well suited for hardware. The objective of this paper was to present the hardware implementation of Advanced Encryption Standard (AES) algorithm. This paper proposes an efficient solution to combine Rijndael encryption and decryption in one FPGA design, with a strong focus on low area constraints and high throughput. This Rijndael implementation runs its symmetric cipher algorithm using a key size of 128 bits, mode called AES128. We have worked with the pipelining structure and modifications such as merging of Subbytes and Shift Rows, and optimization of each clock cycle to incorporate maximum number of operations etc. have been successfully implemented. The encryption and decryption process of Rijndael algorithm was captured in VHDL language and corresponding FPGA implementation resulted in reduced number of slices (6901) and achieved a data throughput of 38.346 Gbps which is implemented on Xilinx 14.2 Virtex5.