Methodology for MMIC Layout Design

This paper presents a layout design methodology for monolithic microwave integrated circuits, which leads to the optimized layout in a fast and efficient way, avoiding time-consuming computer simulations. The proposed procedure is based on subdividing the layout in simple basic cells that are individually optimized. Optimization of each layout basic cell is performed to compensate for parasitic effects associated to circuit components as well as for the effect of short length transmission lines that are added to layout as interconnections. This procedure points out which components are more troublesome to be manufactured and helps the designer to choose a circuit topology that leads to high fabrication yield. As an application example, the layout design of a 5 to 10 GHz LC band-pass filter is presented.