CMOS VLSI layout synthesis for circuit performance

Very Large Scale Integration (VLSI) layout synthesis is a task of transforming an electrical circuit description into an arrangement of polygons which describes photolithographic masks used in fabricating the chip. The role of Computer-Aided Design (CAD) systems in VLSI layout synthesis is to help the designer find a good layout by quickly exploring as many feasible design alternatives as possible. The three most widely accepted metrics for measuring the quality of a layout are the area occupied by the layout, the power drawn by the circuit implemented, and the maximum signal delay through the circuit. As the feature dimensions scale down with the advances in the fabrication technology, the silicon area becomes a less critical resource, and the ever-increasing desire to push circuits' operating speed to the limits of the highest state of the art of this technology is boosting the importance of the circuit delay metric. This thesis presents a method for synthesizing Complementary Metal-Oxide-Semiconductor (CMOS) VLSI layouts in which the layout is optimized for its timing performance in an area-efficient manner. This approach implemented in a computer program called perflex uses a flexible layout style so as to facilitate fine-grain layout optimizations. The techniques used in perflex for optimizing circuit performance are minimization of wiring parasitics along critical paths, transistor sizing, and transistor reordering. These individual techniques and the way in which they are brought together in a layout synthesis environment are described in the thesis. Experimental results included in the thesis indicate that perflex can significantly improve the timing performance of a circuit design while the layout area required for the design is kept comparable to what can be obtained when the layout is optimized for its area. Also, when compared with the designs based on conventional standard cell place-and-route methodology, perflex-generated layouts are better in all aspects of maximum signal delay, layout area, and power consumption.