A 3.8 GHz programmable gain amplifier with a 0.1 dB gain step

A broadband programmable gain amplifier (PGA) with a small gain step and low gain error has been designed in 0.13 μm CMOS technology. The PGA was implemented with open-loop architecture to provide wide bandwidth. A two-stage gain control method, which consists of a resistor ladder attenuator and an active fine gain control stage, provides the small gain step. A look-up table based gain control method is introduced in the fine gain control stage to lower the gain error. The proposed PGA shows a decibel-linear variable gain from −4 to 20 dB with a gain step of 0.1 dB and a gain error less than ±0.05 dB. The 3-dB bandwidth and maximum IIP3 are 3.8 GHz and 17 dBm, respectively.