2008•ITC-CSCC :International Technical Conference on Circuits Systems, Computers and CommunicationsRequires access

Implementation of a Functional Verification System using SystemC

Myoung-Keun You, Young-Jin Oh, Gi-Yong Song

Abstract

The implementation of a functional verification system using SystemC, system-level design language, is presented in this paper. SystemC is used in system-level design methodology because of the capability of system architectural model description and hardware/software design. The implemented verification system, which consists of various SystemC modules, in this paper can explore design space using SystemC and verify functional correction of progressive refined module in RTL HDL. The functional verification is performed on a simple device-under-test, the transposed FIR filter. Connections between SystemC simulation kernel and HDL simulator are achieved through user-defined system function of HDL simulator and communication channel.

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Key concepts: SystemC, Computer science, Transaction-level modeling, Electronic system-level design and verification, Functional verification, Embedded system, Computer architecture, Kernel (algebra)