2015•Unpublished venueRequires access

A programmable low dropout regulator for delay correction network in DPWM

Jada Harshil, Anil Kumar Gupta

Abstract

This paper presents a programmable low dropout regulator (LDO) with high PSRR. A programmable reference voltage required for LDO regulator has been implemented using a 5-bit digital to analog converter made of capacitive voltage divider network. The LDO regulator's PSRR performance is enhanced using a feed forward circuit. The output voltage of proposed LDO regulator has 32 discrete voltage levels in the range 1-1.2 V for load current in the range 100 μA to 5 mA. The PSRR of the proposed circuit is 89dB. The LDO regulator was designed in UMC 180nm technology. The proposed LDO regulator works with a supply voltage of 1.6 V and has a quiescent current of 23 μA. It can be used for delay matching in DPWM by changing supply voltage of delay elements.

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Available abstract

Key concepts: Low-dropout regulator, Dropout voltage, Power supply rejection ratio, Regulator, Voltage regulator, Voltage divider, Load regulation, Voltage