Towards an Ultra-Low Energy Computation with Asynchronous Circuits

Emerging biomedical applications would benefit from the availability of digital processors with substantially improved energy-efficiency. One approach to realize ultra-low energy processors is to scale the supply voltage aggressively to near or below the transistor threshold, yet the major increase in delay variability under process, voltage and temperature variations combined with the dominance of leakage power makes robust near- and sub-threshold computations and further voltage scaling extremely challenging. This research focuses on the design and implementation of robust and energy-efficient computation architectures by employing an asynchronous self-timed design methodology. A statistical framework is first presented to analyze the energy and delay of CMOS digital circuits considering a variety of timing methodologies. The proposed analysis framework combines variability and statistical performance models, which enables designers to efficiently evaluate circuit performance, and determine the optimal timing strategy, pipeline depth and supply voltage in the presence of variability. Two asynchronous self-timed designs are then implemented. First, a low-energy asynchronous logic topology using sense amplifier-based pass transistor logic (SAPTL) is presented. The SAPTL structure can realize very low energy computation by using low-leakage pass transistor networks at low supply voltages. The introduction of asynchronous operation in SAPTL further improves energy-delay performance without a significant increase in hardware complexity. The proposed self-timed SAPTL architectures provide robust and efficient asynchronous computation using a glitch-free protocol to avoid possible dynamic timing hazards. Second, an asynchronous neural signal processor is presented to dynamically minimize leakage and to self-adapt to process variations and different operating conditions. The self-timed processor demonstrates robust sub-threshold operation down to 0.25V, while consuming only 460nW in a 65nm CMOS technology, representing a 4.4X reduction in power compared to the state-of-the-art designs. The proposed asynchronous design approach enables CMOS circuits to fully benefit from continued technology scaling and realize ultra-low voltage operation, without incurring the leakage and variability issues associated with conventional synchronous implementations.