Asynchronous Design Methodology for an Efficient Implementation of Low power ALU

The paper presents a design technique for implementing asynchronous ALUs with CMOS domino logic and delay insensitive dual rail four-phase logic. It ensures economy in silicon area and potentially for low power consumption. The design has been described and implemented to achieve high performance in comparison with the synchronous and available asynchronous design. The experimental result shows significant reduction in the number of transistors as well as delay