IBM Research Report BOA: The Architecture of a Binary Translation Processor

AbstractHigh frequency design and instruction-level parallelism (ILP) are two keys tohigh performance microprocessor implementation. To achieve these sometimescompetinggoals, the Binary-translation Optimized Architecture(BOA)aimstobringcode translationtechniquesbasedon continuousprofilinginto the mainstream. Ini-tially, code is interpreted to detect code hot spots and gather profile information toguide dynamic optimizations. To achieve compatibility with the established Pow-erPC architecture, a binary translation layer translates PowerPC instructions intosimple VLIW operationprimitives. These primitivesare thenscheduledusingVLIWschedulingtechniquesto a variable length, six issue VLIW/EPIC processor. Binarytranslation eliminates the binary compatibility problem faced by other processors,while dynamic recompilation enables adaptive re-optimization of critical programcode sections and eliminates the need for dynamic scheduling hardware.As a result, the BOA execution platform can be designed for multiple Giga-hertz operation. The hardware execution platform includes novel microarchitec-tural features to eliminate complex stall and exception logic. Special support isalso provided for binary translation in the form of several primitives designed forsystem-level binary translation functions. The data types of the binary translationprocessor are similar to that of the emulated PowerPC architecture to eliminatedata representation issues which could necessitate potentially expensive data for-mat conversion operations. In this work we examine the implications of binarytranslationon processor architectureand software translationand how we supporta very high frequency PowerPC implementation via dynamic binary translation.