A methodology for translating scheduled software binaries onto field programmable gate arrays

Recent advances in embedded communications and control systems are pushing the computational limits of DSP applications, driving the need for hardware/software co-design systems. This dissertation describes the development and architecture of the FREEDOM compiler that translates DSP software binaries to hardware descriptions for FPGAs as part of a hardware/software co-design. We present our methodology for translating scheduled software binaries to hardware, and described an array of optimizations that were implemented in the compiler. Our balanced scheduling and operation chaining techniques show even greater improvements in performance. Our resource sharing optimization generates templates of reoccurring patterns in a design to reduce resource utilization. Our structural extraction technique identifies structures in a design for partitioning as part of a hardware/software co-design. These concepts were tested in a case study of an MPEG-4 decoder. Results indicate speedups between 14-67x in terms of cycles and 6-22x in terms of time for the FPGA implementation over that of the DSP. Comparison of results with another high-level synthesis tool indicates that binary translation is an efficient method for high-level synthesis.