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FUNCTIONAL DELAY CLOCK FAULT MODELS

Eduardas Bareiša, Vacius Jusas, Kęstutis Motiejūnas, Rimantas Šeinauskas

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Abstract

The test can be developed at the functional level of the circuit. Such an approach allows developing the test at the early stages of the design process in parallel with other activities of this process. The problem is to choose the right fault model because the implementation of the circuit is not available yet. The paper introduces three new fault models for synchronous sequential circuits: functional clock at-speed, functional clock static-based and functional clock delay. The introduced models are based on the primary input values, on the primary output values and on the state bits values of the programming prototype. The presented experimental results explore the possibilities of the functional test that is constructed on the base of the static-based fault model to detect the transition and stuck-at faults. The fault coverage of the functional static-based, stuck-at and transition faults corresponds with one another quite well.

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What this paper is about

The test can be developed at the functional level of the circuit. Such an approach allows developing the test at the early stages of the design process in parallel with other activities of this process. The problem is to choose the right fault model because the implementation of the circuit is not available yet. The paper introduces three new fault models for synchronous sequential circuits: functional clock at-speed, functional clock static-based and functional clock delay. The introduced models are based on the primary input values, on the primary output values and on the state bits values of the programming prototype. The presented experimental results explore the possibilities of the functional test that is constructed on the base of the static-based fault model to detect the transition and stuck-at faults. The fault coverage of the functional static-based, stuck-at and transition faults corresponds with one another quite well.

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Available abstract

The test can be developed at the functional level of the circuit. Such an approach allows developing the test at the early stages of the design process in parallel with other activities of this process. The problem is to choose the right fault model because the implementation of the circuit is not available yet. The paper introduces three new fault models for synchronous sequential circuits: functional clock at-speed, functional clock static-based and functional clock delay. The introduced models are based on the primary input values, on the primary output values and on the state bits values of the programming prototype. The presented experimental results explore the possibilities of the functional test that is constructed on the base of the static-based fault model to detect the transition and stuck-at faults. The fault coverage of the functional static-based, stuck-at and transition faults corresponds with one another quite well.

Key concepts: Computer science, Process (computing), Fault (geology), Fault model, Fault coverage, Timing failure, State (computer science), Base (topology)

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