An interconnect-aware delay model for dynamic voltage scaling in NM technologies

Employing microsystems with Dynamic Voltage Scaling (DVS) is an effective design solution to alleviate their energy consumption. The importance of such design technique keeps growing as both high-performance and low-energy consumption are simultaneously desirable. Existing Power Management Units (PMUs) that support DVS, mainly rely on the delay models valid for CMOS logic. In this work, we show that this may result into improper design and utilization of microsystems subject to DVS; as interconnect delay has become the dominant fraction of the total delay. In accordance with this design concern, we propose a modified delay model which encompasses the effect of interconnect parasitic components, and is suitable for accurate modeling, design and execution of DVS performed by PMUs in nanometer (nm) technologies. HSPICE simulations confirm that the proposed delay model is much more accurate when predicting the performance of a 4-section global H-Tree clock distribution network subject to voltage scaling. The error on predicted performance from true delays is reduced by up to a factor of 4.