An accurate and efficient delay model for CMOS gates in switch-level timing analysis

A heuristic switch-level model for calculating the gate delay is described. It is high accuracy due to its SPICE-like integration approach. Only linear circuit elements are considered, resulting in high efficiency. An easy approach for taking the gate-to-source and gate-to-drain capacitances of MOS transistors into consideration is proposed. An effective way to determine the time step is introduced. Preliminary tests indicate that the model is very accurate and fast, which makes it suitable for handling very large designs. Preliminary timing results for several complex CMOS gates show very good accuracy.>