2014Advanced materials researchOpen access

Design of Router Supporting Multiply Routing Algorithm for NoC

Zhan Jiang, Rui Xu, Chang Chun Dong, Lin Hai Cui

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Abstract

Network on Chip(NoC),a new proposed solution to solve global communication problem in complex System on Chip (SoC) design,has absorbed more and more researchers to do research in this area. Due to some distinct characteristics, NoC is different from both traditional off-chip network and traditional on-chip bus,and is facing with the huge design challenge. NoC router design is one of the most important issues in NoC system. The paper present a high-performance, low-latency two-stage pipelined router architecture suitable for NoC designs and providing a solution to irregular 2Dmesh topology for NoC. The key features of the proposed Mix Router are its suitability for 2Dmesh NoC topology and its capability of suorting both full-adaptive routing and deterministic routing algorithm.

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What this paper is about

Network on Chip(NoC),a new proposed solution to solve global communication problem in complex System on Chip (SoC) design,has absorbed more and more researchers to do research in this area. Due to some distinct characteristics, NoC is different from both traditional off-chip network and traditional on-chip bus,and is facing with the huge design challenge. NoC router design is one of the most important issues in NoC system. The paper present a high-performance, low-latency two-stage pipelined router architecture suitable for NoC designs and providing a solution to irregular 2Dmesh topology for NoC. The key features of the proposed Mix Router are its suitability for 2Dmesh NoC topology and its capability of suorting both full-adaptive routing and deterministic routing algorithm.

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Available abstract

Network on Chip(NoC),a new proposed solution to solve global communication problem in complex System on Chip (SoC) design,has absorbed more and more researchers to do research in this area. Due to some distinct characteristics, NoC is different from both traditional off-chip network and traditional on-chip bus,and is facing with the huge design challenge. NoC router design is one of the most important issues in NoC system. The paper present a high-performance, low-latency two-stage pipelined router architecture suitable for NoC designs and providing a solution to irregular 2Dmesh topology for NoC. The key features of the proposed Mix Router are its suitability for 2Dmesh NoC topology and its capability of suorting both full-adaptive routing and deterministic routing algorithm.

Key concepts: Router, Network on a chip, Routing algorithm, Routing (electronic design automation), Latency (audio), Key (lock), Computer science, Embedded system

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