Input buffer planning for network-on-chip router design

System-on-Chip(SoC) designs become more complex nowadays. The communication between processing elements are suffering challenges due to the wiring problem. Networks-on-Chip(NoC) approach was proposed as a promising solution. Buffers are one of the major resources used by the routers. In this paper, an application-specific buffer planning approach that can be used to customize the router design in networks-on-chip(NoC) is presented. More precisely, given the mapping of the target application and the traffic characteristics, the approach can automatically assign the buffer depth for each input channel in different routers across the chip. The experimental results show that the system buffering resources can be utilized more effectively. In contrast with the uniform buffer allocation, about 50% saving in buffering resources can be achieved by automatic buffer allocation using our approach without any reduction in performance.1