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A NAND structured cell with a new programming technology for highly reliable 5 V-only flash EEPROM

R. Kirisawa, S. Aritome, Ryo Nakayama, Tetsuo Endoh, R. Shirota, F. Masuoka

Open publisher page 35 citations

Abstract

A programming technology is proposed to improve the endurance and read retention characteristics of NAND-structured EEPROM cells programmed by Fowler-Nordheim tunneling of electrons. Erasing and writing are accomplished uniformly over the whole channel area instead of nonuniform erasing at the drain. To achieve programming over the whole channel area, a new device structure is also proposed. The high-voltage pulses can be easily generated on a chip from a single 5-V power supply because the direct current due to the avalanche breakdown does not flow. The gate length of the memory transistor is 1.0 μm. Using 1.0 μm rules, the cell size per bit is 11.7 μm2

About this research paper

What this paper is about

A programming technology is proposed to improve the endurance and read retention characteristics of NAND-structured EEPROM cells programmed by Fowler-Nordheim tunneling of electrons. Erasing and writing are accomplished uniformly over the whole channel area instead of nonuniform erasing at the drain. To achieve programming over the whole channel area, a new device structure is also proposed. The high-voltage pulses can be easily generated on a chip from a single 5-V power supply because the direct current due to the avalanche breakdown does not flow. The gate length of the memory transistor is 1.0 μm. Using 1.0 μm rules, the cell size per bit is 11.7 μm2

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OpenAlex reports 35 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

A programming technology is proposed to improve the endurance and read retention characteristics of NAND-structured EEPROM cells programmed by Fowler-Nordheim tunneling of electrons. Erasing and writing are accomplished uniformly over the whole channel area instead of nonuniform erasing at the drain. To achieve programming over the whole channel area, a new device structure is also proposed. The high-voltage pulses can be easily generated on a chip from a single 5-V power supply because the direct current due to the avalanche breakdown does not flow. The gate length of the memory transistor is 1.0 μm. Using 1.0 μm rules, the cell size per bit is 11.7 μm2

Key concepts: EEPROM, EPROM, NAND gate, Flash (photography), Transistor, Non-volatile memory, Quantum tunnelling, Electrical engineering

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