Floating gate memories reliability

Abstract Besides conventional IC failure mechanisms, the floating gate (FG) device reliability is affected by data retention, characteristic of non‐volatile memories, and endurance, typical of electrically erasable arrays. The subjects of this work are EPROM and flash EEPROM, the leading and most promising devices among the FG non‐volatile memories. The degradation mechanisms observed in programming and erasing steps are investigated. EPROM data retention is associated with intrinsic and defect related charge loss with both electronic and ionic processes involved. Experimental results are presented. The reliability problems associated with repeated write/erase cycles are introduced, and their effects on EEPROM endurance discussed. Finally, a fishbone diagram for data retention is proposed. The complexity of technology and the cell scaling down with increasing chip size impose lower failure rate goals and reliability becomes integrated within the manufacturing process.