Sequential analysis for transistor networks including distributed‐constant circuits

Abstract With the recent development of integrated circuit technology, high‐density and high‐speed integrated circuits are produced. Then the wiring capacitance and wiring resistance of the circuit cannot be ignored, and it is necessary to develop a new circuit simulation method considering the parasitic effects of the wiring. The parasitic effect is represented by a distributed‐constant circuit, and a partial differential equation representing the distributed‐constant circuit must be solved to analyze the parasitic effects. When a partial differential equation is discretized by applying the finite‐element method, however, the analysis of the circuit is reduced to the analysis of the higher‐order equation which requires a tremendous computation time and memory capacity. This paper attempts to avoid this problem, and presents a method in which the circuit is analyzed equivalently without increasing the number of unknowns by applying the sequential analysis to replace the distributed‐constant circuit by three resistors and two current sources.