A Problem Reduction Approach for Scheduling Semiconductor Wafer Fabrication Facilities

Most scheduling procedures used in industry are based on the dispatching paradigm, where decisions are made based on the jobs available at the time the machine becomes free. While optimization-based scheduling procedures have repeatedly been shown to yield significantly better schedules under ideal circumstances, their practical implementation is hampered by high computational requirements. We present a problem reduction procedure that allows a workcenter-based global scheduling heuristic to be implemented in very low CPU times. The procedure partitions the workcenters in a fab into heavily loaded and lightly loaded classes and solves the global scheduling problem only for the heavily loaded workcenters. The proposed technique is tested on instances drawn from an International SEMATECH wafer fab model. The proposed problem reduction approach yields superior results with modest computational effort, enabling the practical use of the decomposition heuristic.