Logic design for low-power CMOS circuits

This paper presents the design of low-voltage and low-power CMOS circuits. It is based on a branch-based logic style that provides many benefits. Branch-based logic is presented and compared to other logic styles. Race-free flip-flops as well as complex gate decomposition are introduced and discussed from the low-voltage/low-power point of view. The advantages of branch modelization compared to cell modelization are presented. Logic parallelization used for some basic cell and logic modules such as shift registers is presented.