2009•Unpublished venueRequires access

A high-data-rate low-power BPSK demodulator and clock recovery circuit for implantable biomedical devices

Farzad Asgarian, Amir Masoud Sodagar

Open publisher page 34 citations

Abstract

A novel noncoherent BPSK demodulator is presented for inductively powered biomedical implants. Data demodulation is based on the detection of the rising or falling edge of the digitized received carrier. Ultra low power consumption and high data transmission rate, without increasing the carrier frequency, are accomplished by the outstanding data-rate-to-carrier-frequency ratio of 100%. Thus, the proposed demodulator is especially appropriate for biomedical applications such as cochlear implants and visual prostheses that require high speed data transfer. The circuit is designed in 0.18-mum standard CMOS technology. At a data transmission rate of 20 Mbps, power consumption of the circuit is as low as 310 muW@1.8 V.

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What this paper is about

A novel noncoherent BPSK demodulator is presented for inductively powered biomedical implants. Data demodulation is based on the detection of the rising or falling edge of the digitized received carrier. Ultra low power consumption and high data transmission rate, without increasing the carrier frequency, are accomplished by the outstanding data-rate-to-carrier-frequency ratio of 100%. Thus, the proposed demodulator is especially appropriate for biomedical applications such as cochlear implants and visual prostheses that require high speed data transfer. The circuit is designed in 0.18-mum standard CMOS technology. At a data transmission rate of 20 Mbps, power consumption of the circuit is as low as 310 muW@1.8 V.

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Available abstract

A novel noncoherent BPSK demodulator is presented for inductively powered biomedical implants. Data demodulation is based on the detection of the rising or falling edge of the digitized received carrier. Ultra low power consumption and high data transmission rate, without increasing the carrier frequency, are accomplished by the outstanding data-rate-to-carrier-frequency ratio of 100%. Thus, the proposed demodulator is especially appropriate for biomedical applications such as cochlear implants and visual prostheses that require high speed data transfer. The circuit is designed in 0.18-mum standard CMOS technology. At a data transmission rate of 20 Mbps, power consumption of the circuit is as low as 310 muW@1.8 V.

Key concepts: Demodulation, Data transmission, CMOS, Phase-shift keying, Electronic engineering, Computer science, Transmission (telecommunications), Power consumption

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