ScholarLens Back to search
2011•Unpublished venueRequires access

A novel low-power high-date-rate BPSK demodulator

Bo Wang, H. H. Liu, Ming Jian Zhao, Bin Li

Open publisher page 2 citations

Abstract

A novel binary phase-shift keying (BPSK) demodulator architecture is presented. The design is fully digital and based on trigger receiving. The demodulator can be applied in wireless communications, biological implants, portable facilities because of its low complexity, low power and high data rate. The prototype chip is fabricated in a 0.35-μm CMOS process and the area of the designed circuits is about 0.5 mm2. Measurement results reveal that the designed demodulator consumes only 319 μw power for the data rate of 10.7MHz 1M bit/s, results also show that it can work well to the high data rate of 100MHz 10M bit/s, which is the highest performance of the BPSK demodulator.

About this research paper

What this paper is about

A novel binary phase-shift keying (BPSK) demodulator architecture is presented. The design is fully digital and based on trigger receiving. The demodulator can be applied in wireless communications, biological implants, portable facilities because of its low complexity, low power and high data rate. The prototype chip is fabricated in a 0.35-μm CMOS process and the area of the designed circuits is about 0.5 mm2. Measurement results reveal that the designed demodulator consumes only 319 μw power for the data rate of 10.7MHz 1M bit/s, results also show that it can work well to the high data rate of 100MHz 10M bit/s, which is the highest performance of the BPSK demodulator.

Why it matters

OpenAlex reports 2 citations for this work. Citation counts describe recorded attention and do not establish research quality.

Key contribution

A contribution statement is not available in the OpenAlex record.

Method / approach

Method details are not available in the OpenAlex metadata.

Main findings

Findings are not separately available in the OpenAlex metadata.

Limitations

Limitations are not available in the OpenAlex metadata.

Applications

Application details are not available in the OpenAlex metadata.

Available abstract

A novel binary phase-shift keying (BPSK) demodulator architecture is presented. The design is fully digital and based on trigger receiving. The demodulator can be applied in wireless communications, biological implants, portable facilities because of its low complexity, low power and high data rate. The prototype chip is fabricated in a 0.35-μm CMOS process and the area of the designed circuits is about 0.5 mm2. Measurement results reveal that the designed demodulator consumes only 319 μw power for the data rate of 10.7MHz 1M bit/s, results also show that it can work well to the high data rate of 100MHz 10M bit/s, which is the highest performance of the BPSK demodulator.

Key concepts: Demodulation, Phase-shift keying, Computer science, Bit error rate, Keying, CMOS, Electronic engineering, Binary number

Related papers

Related paper 1Related paper 2
Back to paper searchBrowse research topicsOriginal source
A novel low-power high-date-rate BPSK demodulator — Research Paper | ScholarLens