Design of a wave-pipelined serializer-deserializer with an asynchronous protocol for high speed interfaces

In this paper, we proposed an asynchronous wave-pipelined Serializer and Deserializer, or WP-SERDES in brief, that is totally clock-free. In contrast to conventional SERDES that employ power hungry phase-locked loops (PLLs) for synchronization in serializers and clock-data recovery (CDR) circuits in deserializers, the proposed WP-SERDES employs delay elements (DEs) consisting of inverter chains for timing reference. Besides, throughput of the proposed WP-SERDES is adjustable thanks to the voltage-controlled inverters used in the DEs. The proposed WP-SERDES which was simulated using 180nm CMOS process shows a 3.9 Gb/s throughput and 2.44 mW power consumption.