Research on Design for Testability of PCB Based on JTAG

Design principle and methodology of DFT in BST are discussed ,fault models of interconnect on a circuit board and equivalent exchange are done in order to simplify test process. Mathematical models of BST are established also in this thesis. Based on above principle and methodology, test stimuli generation and test response analysis of boundary scan interconnect test are studied .Two optimal boundary scan interlink age test algorithms are presented. Using DFT methodology of boundary scan, DFT of circuit board is finished, by two optimal algorithms, test effectiveness and correctness is validated.