Tutorial on design for testability (DFT) "An ASIC design philosophy for testability from chips to systems"

This is a comprehensive tutorial on DFT with emphasis on concepts of digital Application Specific Integrated Circuit (ASIC) testing incorporating boundary scan architecture in ASIC design. This tutorial covers discussion and features of Institute of Electrical and Electronics Engineers (IEEE) Standard 1149.1, Joint Test Action Group (JTAG) test technique, that can be implemented during design and development of digital ASIC and systems. These test techniques can be applied to test device mounted multi-layer Printed Circuit Boards (PCBs) and Multi Chip Modules (MCMs).>