2002Unpublished venueRequires access

A new adaptive resurf concept for 20 V LDMOS without breakdown voltage degradation at high current

K. Kinoshita, Yoshimasa Kawaguchi, A. Nakagawa

Open publisher page 28 citations

Abstract

This paper presents a new adaptive resurf (reduced surface field) concept for 20 V LDMOS which introduces an additional resurf layer to the conventional resurf layer. The new resurf LDMOS achieves a sufficiently low on-resistance of 17.7 m/spl Omega//spl middot/mm/sup 2/ and a high static breakdown voltage of 28.0 V without significant breakdown voltage degradation under large drain current flow conditions. The device on-state breakdown voltage for a 5 V gate voltage is 21.8 V.

About this research paper

What this paper is about

This paper presents a new adaptive resurf (reduced surface field) concept for 20 V LDMOS which introduces an additional resurf layer to the conventional resurf layer. The new resurf LDMOS achieves a sufficiently low on-resistance of 17.7 m/spl Omega//spl middot/mm/sup 2/ and a high static breakdown voltage of 28.0 V without significant breakdown voltage degradation under large drain current flow conditions. The device on-state breakdown voltage for a 5 V gate voltage is 21.8 V.

Why it matters

OpenAlex reports 28 citations for this work. Citation counts describe recorded attention and do not establish research quality.

Key contribution

A contribution statement is not available in the OpenAlex record.

Method / approach

Method details are not available in the OpenAlex metadata.

Main findings

Findings are not separately available in the OpenAlex metadata.

Limitations

Limitations are not available in the OpenAlex metadata.

Applications

Application details are not available in the OpenAlex metadata.

Available abstract

This paper presents a new adaptive resurf (reduced surface field) concept for 20 V LDMOS which introduces an additional resurf layer to the conventional resurf layer. The new resurf LDMOS achieves a sufficiently low on-resistance of 17.7 m/spl Omega//spl middot/mm/sup 2/ and a high static breakdown voltage of 28.0 V without significant breakdown voltage degradation under large drain current flow conditions. The device on-state breakdown voltage for a 5 V gate voltage is 21.8 V.

Key concepts: LDMOS, Breakdown voltage, Electrical engineering, Materials science, Degradation (telecommunications), Voltage, Power MOSFET, High voltage

Related papers

Back to paper searchBrowse research topicsOriginal source
A new adaptive resurf concept for 20 V LDMOS without breakdown voltage degradation at high current — Research Paper | ScholarLens