Novel strategies of FSG-CMP for within-wafer uniformity improvement and wafer edge yield enhancement beyond 0.18 micro technologies

Low-k films and higher multiple stacked layers are likely to be widely applied for ULSI circuits. However, for 8" (200 mm) or 12" (300 mm) wafers, wafer edge collapse phenomena in higher interlayer low-k film occurs due to CMP polishing effects. Work has been developed for the optimization of different polishing parameters and polishing head design in order to resolve these problems, but these methods failed to address the theory of edge collapse in CMP and its control. In this paper, we discuss the theory applied in the Preston equation to explain the wafer edge polishing behavior. In order to implement the theory, we adopted novel strategies, including different polishing head (sweep) vibration and pad edge sprayer methods, new wafer retaining ring design and novel slurry delivery methods. The within wafer nonuniformity and edge profile characteristics of CMP polished low-k films of fluorinated silicate glass (FSG) were evaluated under this new strategy. In addition, the metal line and via dimensions, and edge die-yield directly responded to the edge profile improvement. An average 7-10% yield improvement of 0.18 /spl mu/m technology can be achieved, with up to 15% edge-die yield improvement. The edge profile prevented collapse from the original 75 mm to up to 95 mm of wafer center-to-edge distance, excluding the 3 mm edge of an 8-inch wafer. These efficient strategies for within-wafer planarization and edge profile were also proven by the reduction of via CD deviation by over 50% under lithography rules.