1978IEEE Journal of Solid-State CircuitsRequires access

Propagation delay time and delay-power product of a small-sized DSA-ED gate circuit

Y. Hayashi

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Abstract

First-order estimation by the simple scaling concept on a DSA-ED (diffused self-aligned enhancement-depletion) gate circuit is described. Propagation delay time less than 100 ps and delay-power product less than 1 fJ will be obtained by an ED NOR gate with DSA MOS drivers with 0.2 /spl mu/ source-to-drain distance and 200 /spl Aring/ gate oxide thickness.

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What this paper is about

First-order estimation by the simple scaling concept on a DSA-ED (diffused self-aligned enhancement-depletion) gate circuit is described. Propagation delay time less than 100 ps and delay-power product less than 1 fJ will be obtained by an ED NOR gate with DSA MOS drivers with 0.2 /spl mu/ source-to-drain distance and 200 /spl Aring/ gate oxide thickness.

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Available abstract

First-order estimation by the simple scaling concept on a DSA-ED (diffused self-aligned enhancement-depletion) gate circuit is described. Propagation delay time less than 100 ps and delay-power product less than 1 fJ will be obtained by an ED NOR gate with DSA MOS drivers with 0.2 /spl mu/ source-to-drain distance and 200 /spl Aring/ gate oxide thickness.

Key concepts: Propagation delay, Power–delay product, Delay calculation, Electrical engineering, Gate oxide, Power (physics), Logic gate, Scaling

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