Interconnection Delay in Very

Interconnection delay of VLSI has been a major concern in the design of high-speed digital systems. This prob- lem becomes even more pronounced as the minimum feature size is scaled down to the submicron level, and the transistor's intrinsic switching time is decreased well into the subnanosec- ond range (11-(61. This paper presents a formal analysis of the signal propagation delay in VLSI circuits. We show that, de- pending upon the circuit parameters, there are basically two delay domains: RC delay domain and transmission-line-delay domain, The results derived from the more traditional lumped- RC model mainly capture the properties of the RC delay do- main. However, in the transmission-line-delay domain the wire inductance becomes an important factor, and hence RC model- ing is no longer adequate to estimate the delay (71-(101. Two delay formulas are respectively derived in this paper for the RC delay domain and the transmission-line-delay domain. The ef- fect of feature size scaling on VLSI circuit performance is also evaluated, and the inherent limitation on scaling due to inter- connection delay is discussed. Finally, the relationship between delay and technology parameters, such as wire resistance, ca- pacitance, inductance, wire width and length, and load capaci- tance, is investigated to provide design guidelines.