2005•Unpublished venueOpen access

Gate current in stacked dielectrics for advanced FLASH EEPROM cells

F. Driussi, S. Marcuzzi, Pierpaolo Palestri, L. Selmi

Abstract

This paper presents a simulation study of the gate current through stacked dielectrics of interest for advanced nonvolatile memory (NVM) cells possibly employing high-k insulators to engineer the tunnel barrier. Program, retention and read disturb conditions are analyzed. The impact of modeling approximations on the predictions of the programming gate current in Fowler-Nordheim (FN) and channel hot electron (CHE) injection regimes is critically discussed. Comparison with a reference SiO/sub 2/ device allows us to identify some of the possible advantages and limitations of these stacks for future NVM.

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Key concepts: EEPROM, Non-volatile memory, EPROM, Flash (photography), Materials science, Flash memory, Hot-carrier injection, Optoelectronics