2007•Unpublished venueRequires access
A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications
Yih Wang, Jiefeng Lin, Yat Hon Ng, I. Post, Lin Wei, Yu Zhang, Kedong Zhang, Mark T. Bohr, Hong Jo Ahn, Uma Bhattacharya, Tom Coan, Fatih Hamzaoglu, W. Hafez, C.-H. Jan, P. Kolar, Sarvesh H. Kulkarni
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Abstract
A low-power high-speed SRAM macro is implemented in an ultra-low-power 8M 65nm CMOS for mobile applications. The 1Mb macro features a 0.667μm2low-leakage memory cell and operates with supply voltage from 0.5V to 1.2V. It operates at a frequency of 1.1 GHz at 1.2V and 250MHz at 0.7V. Leakage is reduced to 12μA/Mb at the data retention voltage of 0.5V. The measured bitcell leakage from the SRAM array is ~2pA/b at retention voltage with integrated leakage reduction schemes.