Impact of oxide thickness on performances of logic circuits: a predictive simulation study

This paper investigates the role that the gate oxide thickness (Tox) plays on power and delay behaviors of logic circuits. Static and dynamic CMOS logic gates have been considered as benchmarks. To extend the predictive simulation study here presented to future technologies, Berkeley Predictive Technology Models (BPTM) have been used. From a circuit perspective, simulation results showed that the optimal Tox is larger than the nominal value, usually obtained from a device perspective.