A 28nm 360ps-access-time two-port SRAM with a time-sharing scheme to circumvent read disturbs

With the rapid growth in the market for mobile information terminals such as smart phones and tablets, the performance of image processing engines (e.g., operation speed, accuracy in digital images) has improved remarkably. In these processors, 2-port SRAM (2P-SRAM) macros, in which a read port and a write port are operated synchronously in a single clock cycle, are widely used. Since the 2P-SRAM is placed in front of large scale logic circuitry for image processing, a faster access time (e.g., <;1 ns) is required. In general, the read-out operation in 2P-SRAM utilizes full-swing of the single read bitline (BL), so a drastic improvement of the access time is not expected. On the other hand, the dual-port SRAM (DP-SRAM) makes use of the voltage difference between BL pair in the read-out operation, which is suitable for the high-speed operation. In this study, we present a time-sharing scheme using a DP-SRAM cell to achieve high-speed access in 2P-SRAM macros in such image processors.