An address access time measurement method for high‐speed mos static rams

Abstract With the advance of a high‐speed MOS static RAM (SRAM), it is considered a problem to measure the access time of SRAM more accurately. In the measurement of the address access time, it is assumed that a large number of address signals are all simultaneously forced on SRAM. In the actual measurement of SRAM, however, it is difficult to determine the forcing time of the address signals at the input of SRAM. Consequently, the foregoing condition is difficult. This paper considers the measurement of the address access time of the high‐speed SRAM and proposes a method whereby the forcing time of the address signal can easily be measured and corrected on the memory tester. In the method, the GND bounce generated in SRAM itself in response to the given address signal is measured in the reference SRAM. Then the variation of the address signal forcing time is evaluated quantitatively and corrected. The proposed method is applied to a commercial memory tester to measure the address access time in 64‐kbit CMOS SRAM with the maximum access time of 15 ns. As a result, the variation of the address signal forcing time is kept within ±100 ps, and the measurement error of the SRAM address access time with different testers is within 1 ns, which is satisfactory.