[Paper] Digital Calibration for a 2-Stage Cyclic Analog-to-Digital Converter Used in a 33-Mpixel 120-fps SHV CMOS Image Sensor

A digital calibration algorithm is proposed for a 2-stage cyclic analog-to-digital converter (ADC) with 12-bit resolution used in a 33-Mpixel 120-fps CMOS image sensor for Super High-Vision. This algorithm can correct errors generated in the ADC due to capacitor mismatch, finite gain error, and incomplete settling error. A simulation was performed to verify the proposed algorithm. The results show that the maximum differential nonlinearity (DNL) is improved to +0.49 / -0.48 LSB from +4.5 / -1.5 LSB, and the maximum integral nonlinearity (INL) is improved to +0.23 / -0.27 LSB from +7.5 / -1.5 LSB.