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2010•IEEE Transactions on NanotechnologyRequires access

A Novel Capacitorless 1T DRAM Cell for Data Retention Time Improvement

Woojun Lee, Woo Young Choi

Open publisher page 24 citations

Abstract

This paper proposes a silicon-with-partially-insulating-layer-on-silicon-on-insulator (SISOI) one-transistor dynamic random access memory (1T DRAM) cell to increase data retention time. A conventional 1T DRAM cell has a data retention problem because it stores holes in an SOI layer, which is not separated from the source/drain region. However, the proposed SISOI 1T DRAM cell can keep holes electrically separated from the source/drain region, which leads to the increase of data retention time.

About this research paper

What this paper is about

This paper proposes a silicon-with-partially-insulating-layer-on-silicon-on-insulator (SISOI) one-transistor dynamic random access memory (1T DRAM) cell to increase data retention time. A conventional 1T DRAM cell has a data retention problem because it stores holes in an SOI layer, which is not separated from the source/drain region. However, the proposed SISOI 1T DRAM cell can keep holes electrically separated from the source/drain region, which leads to the increase of data retention time.

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OpenAlex reports 24 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

This paper proposes a silicon-with-partially-insulating-layer-on-silicon-on-insulator (SISOI) one-transistor dynamic random access memory (1T DRAM) cell to increase data retention time. A conventional 1T DRAM cell has a data retention problem because it stores holes in an SOI layer, which is not separated from the source/drain region. However, the proposed SISOI 1T DRAM cell can keep holes electrically separated from the source/drain region, which leads to the increase of data retention time.

Key concepts: Dram, Data retention, Dynamic random-access memory, Silicon on insulator, Transistor, Optoelectronics, Silicon, Materials science

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