Novel 2T gain cell with enhanced retention time for embedded DRAM application

A high performance 2T gain cell memory device is demonstrated for the first time in 0.13μm CMOS technology. A novel asymmetric source and drain doping profile combined with high threshold voltage (Vt) scheme for the write transistor is introduced to reduce the cell leakage and then improve data retention characteristics. Experimental results show a data retention of 698μs @85°C with 99.9% yield, which proves that the proposed 2T gain cell may be a very promising candidate for low cost and high density eDRAM application.