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2002•Unpublished venueRequires access

Delay-modeling of NAND gates

Srikanth Vemuru, A.R. Thorbjornsen

Open publisher page 2 citations

Abstract

A model for evaluating the propagation delay, rise and fall time of NAND gates is proposed. The model includes the shape of the input waveform, the capacitive load, and the transconductances of the NMOS and the PMOS transistors. The effect of the position of the first active input is included in the model. The proposed model is compared with SPICE for accuracy and computation speed.>

About this research paper

What this paper is about

A model for evaluating the propagation delay, rise and fall time of NAND gates is proposed. The model includes the shape of the input waveform, the capacitive load, and the transconductances of the NMOS and the PMOS transistors. The effect of the position of the first active input is included in the model. The proposed model is compared with SPICE for accuracy and computation speed.>

Why it matters

OpenAlex reports 2 citations for this work. Citation counts describe recorded attention and do not establish research quality.

Key contribution

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Method / approach

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Available abstract

A model for evaluating the propagation delay, rise and fall time of NAND gates is proposed. The model includes the shape of the input waveform, the capacitive load, and the transconductances of the NMOS and the PMOS transistors. The effect of the position of the first active input is included in the model. The proposed model is compared with SPICE for accuracy and computation speed.>

Key concepts: NMOS logic, PMOS logic, NAND gate, Spice, Waveform, Computer science, Logic gate, Propagation delay

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