On-line testing of multi-source noise-induced errors on the interconnects and buses of system-on-chips

With processors and system-on-chips using nano-meter technologies, several design and test efforts have been recently developed to eliminate and test for many emerging DSM (deep sub-micron) noise effects. In this paper, we show the emergence of multi-source noise effects, where multiple DSM noise sources combine to produce functional and timing errors even when each separate noise source itself does not. We show the dynamic nature of multi-source noise, and the need for on-line testing to detect such noise errors. We propose a double-sampling data checking based low-cost on-line error detection circuit to test for such noise effects in on-chip buses. Based on the proposed circuit, an effective and efficient testing methodology has been developed to facilitate online testing for generic on-chip buses. The applicability of this methodology is demonstrated through embedding the on-line detection circuit in a bus design. The validated design shows the effectiveness of the proposed testing methodology for multi-source noise-induced errors in global interconnects and buses.