A trace based evaluation of speculative branch decoupling

Branches are one of the main impediments to achieving maximum instruction-level parallelism. Branch prediction along with speculative execution is the main, incumbent methodology to hide branch stalls. Branch decoupled architectures offer an alternate way of reducing branch penalty. This paper presents a combination of the two methodologies, to show that they can coexist and may provide better performance than processors with conventional branch prediction techniques, but equivalent hardware resources. A trace based evaluation is presented, and with three different branch prediction techniques, it is shown that over twelve of the SPEC'95 CPU benchmarks, speculative branch decoupling performs significantly better than branch prediction with speculative execution, in all the cases. Since a trace based approach has its limitations, the study is a limited one, but makes a strong case for further research in this area.