Branch prediction methods used in modern superscalar processors

Branch prediction is crucial to maintaining high performance in modern superscalar processors. Conditional branches can occur as frequently as one in every 5 or 6 instructions in nonnumeric programs, leading to heavy mis-prediction penalties in current superpipelined, superscalar architectures. Realization of this fact has lead to an upsurge in the number of recent research publications in this area. This has been accompanied by the processor manufacturers implementing more complex branch prediction hardware in recent processors. This paper surveys the status of research in static and dynamic branch prediction and also how these research findings are being employed by current processor designers. The paper ends with an evaluation of future directions of branch prediction.