Comparative ADC performance evaluation using a new emulation model for flash ADC architectures

This paper investigates various flash A/D converters (ADC's) using a new emulation model which mimics the gate-level architecture of a flash ADC with any number of bits, n. The model is used for studying the effects of noise and offset voltages at the comparator inputs on the ADC output deviation using a mean-square error criterion. The first ADC investigated is the full-flash one, which is compared with the successive-approximation ADC for the same n. Then, two-step flash ADC's (i.e. half-flash) are investigated, with and without an interstage gain. Finally, error correction is attempted in conjunction with the later half-flash type.