2008•Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits ConferenceRequires access
A 9.4-ENOB 1V 3.8¿W 100kS/s SAR ADC with Time-Domain Comparator
Andrea Agnes, Edoardo Bonizzoni, P. Malcovati, Franco Maloberti
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Abstract
The ADC-SAR is fabricated in a 0.18mum 2P5M CMOS process. This SAR-ADC converter achieves 56fJ/conversion-step FOM with 58dB SNDR. It uses a comparator, named time-domain comparator, that instead of operating in the voltage domain, transforms the input and the reference voltages into pulses and compares their duration.