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An Efficient Rule Based Fault Simulator

Oommen Tharakan, J. Jacob, Madana Srinivas

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Abstract

In this paper, we report the successful development and implementation of a new fast fault simulation algorithm called Rule Based Fault Simulation. This algorithm is based on a set of rules for deducing the fault list at every line of a digital combinational circuit. The fault simulator has been implemented in the C programming language. The implementation consists of about 3000 lines of source code. The simulator incorporates a three valued (0, 1, x) logic sirnulation and a rule based fault propagation technique. The results of this Rule Based Fault Simulator have been compared with that of an existing Concurrent fault simulator available at Indian Institute of Science, Bangalore. The results obtained for ISCAS-85 benchmark circuits have shown that this simulator is more eficient, than the concurrent fault simulator in terms of CPU time and memory.

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What this paper is about

In this paper, we report the successful development and implementation of a new fast fault simulation algorithm called Rule Based Fault Simulation. This algorithm is based on a set of rules for deducing the fault list at every line of a digital combinational circuit. The fault simulator has been implemented in the C programming language. The implementation consists of about 3000 lines of source code. The simulator incorporates a three valued (0, 1, x) logic sirnulation and a rule based fault propagation technique. The results of this Rule Based Fault Simulator have been compared with that of an existing Concurrent fault simulator available at Indian Institute of Science, Bangalore. The results obtained for ISCAS-85 benchmark circuits have shown that this simulator is more eficient, than the concurrent fault simulator in terms of CPU time and memory.

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Available abstract

In this paper, we report the successful development and implementation of a new fast fault simulation algorithm called Rule Based Fault Simulation. This algorithm is based on a set of rules for deducing the fault list at every line of a digital combinational circuit. The fault simulator has been implemented in the C programming language. The implementation consists of about 3000 lines of source code. The simulator incorporates a three valued (0, 1, x) logic sirnulation and a rule based fault propagation technique. The results of this Rule Based Fault Simulator have been compared with that of an existing Concurrent fault simulator available at Indian Institute of Science, Bangalore. The results obtained for ISCAS-85 benchmark circuits have shown that this simulator is more eficient, than the concurrent fault simulator in terms of CPU time and memory.

Key concepts: Fault Simulator, Benchmark (surveying), Fault (geology), Computer science, Logic simulation, Set (abstract data type), Fault model, Computer architecture simulator

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