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A novel high CMRR low voltage current output stage

Mohammad Hekmat Kashtiban, Seyed Javad Azhari

Open publisher page 10 citations

Abstract

In this work a novel CMOS current output stage (COS) is presented whose common-mode rejection ratio is remarkably increased exploiting a novel common mode feed forward (CMFF) technique to compensate the output common mode signal. The complete stage is designed in 0.13 mum technology and simulated with ADS and Hspice. The proposed COS achieved 105 dB CMRR and 85 dB PSRR while can work under plusmn1 V power supply. Compared to the traditional COS the CMRR and PSRR improvement are higher than 50 dB and 30 dB respectively.

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What this paper is about

In this work a novel CMOS current output stage (COS) is presented whose common-mode rejection ratio is remarkably increased exploiting a novel common mode feed forward (CMFF) technique to compensate the output common mode signal. The complete stage is designed in 0.13 mum technology and simulated with ADS and Hspice. The proposed COS achieved 105 dB CMRR and 85 dB PSRR while can work under plusmn1 V power supply. Compared to the traditional COS the CMRR and PSRR improvement are higher than 50 dB and 30 dB respectively.

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Available abstract

In this work a novel CMOS current output stage (COS) is presented whose common-mode rejection ratio is remarkably increased exploiting a novel common mode feed forward (CMFF) technique to compensate the output common mode signal. The complete stage is designed in 0.13 mum technology and simulated with ADS and Hspice. The proposed COS achieved 105 dB CMRR and 85 dB PSRR while can work under plusmn1 V power supply. Compared to the traditional COS the CMRR and PSRR improvement are higher than 50 dB and 30 dB respectively.

Key concepts: Power supply rejection ratio, Common-mode rejection ratio, CMOS, Common-mode signal, Current mirror, Electronic engineering, Voltage, Electrical engineering

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