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1990•European Design Automation ConferenceRequires access

A system for floorplanning with hierarchical placement and wiring

Kevin McCullen, John Thorvaldson, David DeMaris, Patrick Lampin

Open publisher page 6 citations

Abstract

Hierarchical physical design is essential for large VLSI chips. This paper describes a new efficient floorplanning system designed to work within a hierarchical design environment; it supports either 'strict' or 'pseudo'-hierarchy, and multiple design styles. The authors have demonstrated that their mix of interactive and automatic floorplanning tools allows users to significantly improve the control of timing and wirability on VLSI designs. >

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What this paper is about

Hierarchical physical design is essential for large VLSI chips. This paper describes a new efficient floorplanning system designed to work within a hierarchical design environment; it supports either 'strict' or 'pseudo'-hierarchy, and multiple design styles. The authors have demonstrated that their mix of interactive and automatic floorplanning tools allows users to significantly improve the control of timing and wirability on VLSI designs. >

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OpenAlex reports 6 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

Hierarchical physical design is essential for large VLSI chips. This paper describes a new efficient floorplanning system designed to work within a hierarchical design environment; it supports either 'strict' or 'pseudo'-hierarchy, and multiple design styles. The authors have demonstrated that their mix of interactive and automatic floorplanning tools allows users to significantly improve the control of timing and wirability on VLSI designs. >

Key concepts: Floorplan, Very-large-scale integration, Physical design, Computer science, Hierarchy, Computer architecture, Integrated circuit layout, Integrated circuit design

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